I have just finished pcie partial reconfiguration (PR) design on Xilinx Virtex 6 FPGA. Now right after computer powerup only small part of FPGA becomes configured from flash with small static part that contains pcie core and interface logic to internal configuration access port (ICAP). During BIOS PCIe bus scan our FPGA becomes dicovered and memory resources are assigned to it. After complete OS load user application can access FPGA by pcie interface and transfer there partial bit file for unconfigured region.
IMHO there are at least 3 reasons to use this approach to FPGA configuration in scenario when FPGA is connected to computer host by PCIe bus:
- FPGAs become bigger every year and size of bit files grows also. It implies that to use these modern FPGAs you need bigger flash memory device all the time, which may be a problem - for example there is no such dense SPI flash memory chips on the market. PR can solve this problem, because only small static configuration file should be stored in flash in this case.
- While configuration file length rises so does the configuration time. And as stated by PCIe specification all pcie devices should be up and running and able to answer on BIOS configuration requests within 100 ms after computer powerup. Very often it is very tight limit for large FPGAs and PR approach can also help because it takes much less to for initial configuration to complete.
- Also this approach helps a lot when there is a need to reconfigure FPGA while computer is running. For example in high performance computing (HPC) field.
So you should you do to use PR over PCIe in your next design?
First, check out Xilinx Application note on this topic xapp883_Fast_Config_PCIe. It is a good starting point.
Also you will need to learn how to use Xilinx PlanAhed software that supports PR design flow. I suggest you master Partial Reconfiguration User Guide UG702 which will help get aware of general partial reconfiguration process and give you some experince in using PlanAhead.
On design entry level you will have to follow several rules, for example you will definatelly want to insert additional registers on all signals that cross partition boundary on both sides of it. It is needed to preserve timing, which is always an issue in design with partitions. Check Hierarchical Design Methodology Guide UG748 for more details on design flow with partitions.