C to RTL Synthesis

Hi again 

I want to post some update on current work. Right now me and collegues from Institute of System Programming am working on developing a system for our hardware  (FPGA project + system level code) capable of running calculations based on different C to RTL Synthesis tools. 

For now we are focusing on Open Source projects like ROCCC and C-to-Verilog (CTV). Both tools generate RTL code that can be inserted into FPGA project. The hardware interface is not very difficult to integate and depends on the C function prototype or interface. Imagine you have a C fucntion like

void my_func(int* Ain, int* Bout)

Where Ain and Bout are arrays of data you whant to process inside the function. When translated to RTL this  function will have a simple interface to memory: two ports (one per array) to static like (BRAM for example) memory will be generated. Besides that some simple control interface (reset, start and done signals) will be generated.

So as applied programmer you have to
1. Load data to memory from host
2. Connect memory to C-to-RTL circuit and send command to start calculations
3. After calc is finished fetch data from memory to host

Comparing ROCCC and CTV tools I can say that ROCCC generates more optimised RTL, but implies more restrictions on your C code.

The work is just started and there is a lot yet to be done, so I better get back to work :))